Field of the Invention
Embodiments of the present invention relate generally to graphics processing and, more specifically, to two pass cache tile processing for visibility testing in a tile-based architecture.
Description of the Related Art
Graphics processing subsystems typically write depth information to a depth buffer that stores depth information for samples and pixels. When the graphics subsystem processes fragments, the graphics processing system compares depth values associated with those fragments with the depth values stored in the depth buffer. This comparison is referred to as a “z-test.” For any particular fragment, if the z-test is successful and the fragment is visible, then the fragment is written to the frame buffer or blended with color data already in the frame buffer. If, on the other hand, the fragment does not pass the visibility test, then the fragment is discarded.
Some graphics processing subsystems additionally include a z-cull unit and an early-z unit that are configured to perform early visibility tests on fragments prior to shading the fragments. Such early visibility testing allows non-visible fragments to be discarded prior to fragment shading, which saves the processing cycles and power associated with shading fragments that ultimately would be discarded during z-testing.
Some graphics processing subsystems implement a tile-based architecture, where one or more render targets, such as a frame buffer, are divided into screen space partitions referred to as “tiles.” In such a tile-based architecture, the graphics processing subsystem rearranges work such that the work associated with any particular tile remains in an on-chip cache for a longer time than with an architecture that does not rearrange work in this manner. This rearrangement helps to improve memory bandwidth as compared with a non-tiling architecture.
Some conventional tiling architectures perform visibility testing before pixel shading to reduce overdraw. However, many of these conventional tiling architectures introduce latency associated with reading the depth data necessary for the visibility testing operations.
As the foregoing illustrates, what is needed are more effective techniques for discarding non-visible pixels in a tile-based architecture.